# Example Makefile to copy and edit for your own use # make: build .d, .o, and executable target # make clean: remove built files # compiler CC = gcc # compiler flags CFLAGS = -Wall -g # include paths: # define any non-default paths to header files (.h) used by this program # (default location, /usr/include/, is searched by gcc last) INCLUDES = -I../includes -I. # preprocessor flags # these flags create dependency files (.d) for all SRCS CPPFLAGS = -MD -MP $(INCLUDES) # library paths # define any non-default paths to where libraries used by the program may be # (default location, /usr/lib/, is searched by gcc last) LFLAGS = -L../lib -L/home/newhall/lib # define libraries to link into executable # -lm: std math library in /usr/lib (named libm.so or libm.a) # -lmylib: is a library not in standard location, so -L paths # are used to find it (named libmylib.so or libmylib.a) LIBS = -lm -lmylib # set of source files # (\ is the line continuation character) SRCS = emitter.c init.c lexer.c symbol.c parser.c ast.c \ error.c symbol_table.c codegen.c emitcode.c main.c # set of object files # obtained from SRCS using suffix replacement rule OBJS = $(SRCS:.c=.o) # executable file name TARGET = mycc # .PHONY tells make that these targets are not file names but # the target labels for a set of commands to run when `make [target label]` # is invoked (e.g., `make clean` executes a `rm` command) # .PHONY: clean # the rest of this is generic and should not need to be edited: all: $(TARGET) $(TARGET): $(OBJS) $(CC) $(CPPFLAGS) $(CFLAGS) $(INCLUDES) -o $(TARGET) $(OBJS) $(LFLAGS) $(LIBS) # just use make's built-in rule (.c.o:) to build .o from .c files! clean: $(RM) *.o *~ $(TARGET) *.d # include the dependency files here # this uses a suffix replacement within a macro $(name:string1=string2): # (for each word in 'name' replace 'string1' with 'string2') # here we replace the suffix .c with .d for every name in SRCS # # the '-' before 'include' supresses error messages when a .d file # doesn't already exist -include $(SRCS:%.c=%.d)